1. Field of the Invention
The present invention relates to a cell-library-for-statistical-timing-analysis creating apparatus and a statistical-timing analyzing apparatus.
2. Description of the Related Art
In recent years, microminiaturization of semiconductor integrated circuits has been advanced and delay variation due to manufacturing variation tends to increase according to the advance in the microminiaturization. Therefore, timing analysis with the delay variation accurately taken into account is becoming necessary and indispensable.
As a method of efficiently performing the timing analysis with the delay variation accurately taken into account, there is a statistical timing analysis. A cell library for statistical timing analysis is necessary to execute the statistical timing analysis. However, time required for creating the library is extremely long.
To cope with this problem, a plurality of methods of reducing library creation time have been proposed. For example, Japanese Patent Application Laid-Open No. 2008-112406 discloses a method of dividing a cell into a plurality of partial circuits and performing characterization for each of the partial circuits. In this method, when the same partial circuit is included in a plurality of cells, the partial circuit only has to be characterized once. Therefore, characterization time can be reduced. For example, each of an AND gate with one-fold driving force and an AND gate with four-fold driving force can be divided into two partial circuits in a pre-stage and a post-stage. However, since partial circuits in pre-stages of the AND gates are the same, when the AND gate with one-fold driving force is characterized, characterization for the pre-stage of the AND gate with four-fold driving force is unnecessary.
However, according to the technology disclosed in Japanese Patent Application Laid-Open No. 2008-112406, the characterization time can be reduced only for cells having completely the same partial circuit. Therefore, the effect of the reduction in the characterization time is limited. For example, usually, inverter gates with one-fold driving force, two-fold driving force, and four-fold driving force cannot be divided into smaller partial circuits. Therefore, the characterization time cannot be reduced by this method.
As another method of reducing the characterization time, United States Patent Application Publication No. 2008/0120584 discloses a method of causing a delay variation ratio f=σ/μ, which is obtained by dividing the delay variation amount by average delay time, to represent a delay variation amount to thereby collectively characterize partial circuits having the same topology once. In this method, because inverter gates with one-fold driving force, two-fold driving force, and four-fold driving force have the same topology, the inverter gates can be collectively characterized once. Therefore, the library creation time can be reduced.
However, according to the technology disclosed in United States Patent Application Publication No. 2008/0120584, the delay variation ratio cannot be accurately characterized. In this technology, a single-value delay variation ratio is calculated for each of cells. However, in general, the delay variation ratio is different depending on input signal transition time and an output load capacitance of a cell. Therefore, when the delay variation ratio is represented by a single value, an error is large. Further, even in partial circuits having the same topology, the delay variation ratio is substantially different if driving force is different. Therefore, in this respect, an error is also large in a library by the technology disclosed in United States Patent Application Publication No. 2008/0120584.